This invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which will be useful when applied to a semiconductor integrated circuit device of a flip-chip system in which a semiconductor chip is mounted to a substrate through solder bumps.
A multi-layered structure of wirings for improving freedom of wiring design and for reducing wiring delay, i.e. reducing propagation time delay attributable to the length of wiring, has become essential to the technique employed with respect to the achievement of a higher integration density of semiconductor integrated circuit devices For instance, an Al (aluminum) four-layered wiring structure has thus far been accomplished in logic LSIs consisting of bipolar transistors while Al two-layered wiring structure has thus far been accomplished in memory LSIs of a mega-bit (Mbit) class.
Problems which must be solved for realizing a multi-layered wiring structure include, among other things, making the inter-level insulator film(s) flat and also in making reliable the inter-level connection hole(s) (through-hole). Bias sputter technique and SOG (Spin On Glass) technique have been employed to solve the former while an embedding technique of W (tungsten) by selective CVD (chemical vapor deposition) has been used to cope with the latter.
In a semiconductor integrated circuit having a multi-layered wiring structure, a problem which has been of concern (Japanese Patent Laid-Open No. 119749) is that the achieved final dimension of wirings, particularly the wiring width, exhibits a difference between a region of the same wiring layer where the wiring density is high and a region where the wiring density is low because of the proximity effect of a resist film at the time of patterning of the wiring and because of the difference of etching rates when the Al film is etched. To solve this problem, according to the technique employed by the Japanese Patent Laid-Open No. 119749/1985 described above, the wiring density of the same wiring layer is made uniform by disposing a dummy pedestal, which does not function as part of the wiring itself, in a region having a low wiring density.
On the other hand, in logic LSIs such as a gate array and a micro-computer, the number of terminals (input/output pins) for the connection with external circuits has drastically increased in direct relation with the improvements in the multi-functions made and in the higher integration density of the integrated circuit achieved. A wire bonding system, however, which is employed for establishing the connection with the external circuits by connecting the wires to bonding pads disposed at the peripheral portions of the semiconductor chip has substantially reached its limit. Moreover, since problems associated with such a wire bonding system result from the wiring length becoming increased because the wirings of the internal regions are extended to the corresponding bonding pads at the peripheral portions which, furthermore, results in the signal transmission speed being reduced and, therefore, signal transfer being delayed, the system would not be suitable as a packaging system of the logic LSIs for which a high operation speed is required.
For the reasons described above, a so-called "flip-chip system" which connects bumps (salient electrodes) comprised of a solder or the like to the uppermost wiring of the integrated circuit and mounts the chip to a substrate through this bump has drawn increased attention. In accordance with the flip-chip system, the terminals can be disposed not only at the peripheral portions of the chip but also at its internal regions, and the system provides the advantage that the number of pins of the chip can be increased. The flip-chip system is a packaging system suitable for logic LSIs which must operate at a high operation speed because the wiring length can be substantially less than that required by the wire bonding system.
The flip-chip system is described in detail, for example, in "IBM Journal of Research and Development," Vol. 13, No. 3, pp. 239-250. According to this literature, the connection of the solder bump to the wiring of the uppermost layer is conducted in the following way.
First of all, contact holes reaching the Al wiring of the uppermost layer are bored by etching a passivation film, which film is provided for protecting the surface of the chip, and electrode pads are formed. Next, a solder base layer (BLM: Bump Limiting Metallurgy) is formed by laminating sequentially thin films of Cr (chromium), Cu (copper) and Au (gold) on the electrode pad by vacuum deposition in such a manner as to cover the bottom, sidewalls and upper edge of the contact hole. Chromium (Cr), as the lowermost layer of the solder base layer, is disposed as a film which prevents the alloy reaction between the solder bump and the Al electrode pad and determines the outer diameter of the solder bump. Copper (Cu), constituting the intermediate layer of the solder base layer, is disposed in order to improve wettability of the solder bump and to improve the bonding strength with the base layer. Gold (Au), constituting the uppermost layer of the solder base layer, is disposed to prevent corrosion of the Cu layer below it during the machining process of the BLM layer.
Next, a solder film made of a tin (Sn)/lead (Pb) alloy is selectively deposited onto the solder base layer described above and is wetted back inside a reflow furnace to form hemispherical solder bumps.